1. Technical Field
The present invention relates to electronic design automation (EDA). More specifically, the present invention relates to a method and a system for concurrently performing redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including hundreds of millions of transistors, onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to efficiently perform routing in such a large-scale IC chip.
Routing an integrated circuit (IC) chip involves determining routes for metal wires which electrically connect integrated circuit devices to produce circuits that perform desired functions. Large scale IC chips are typically routed using routing software, which is typically referred to as a “routing system” or “router.”
During routing, the system can add vias for interconnecting tracks in adjacent metal layers. When sufficient space is available on a track around a via, an extra via can be introduced to improve manufacturing yield. These extra vias are called “redundant vias,” and the process of adding redundant vias is referred to as “redundant via insertion.” Redundant via insertion is an important Design for Manufacturing (DFM)-related adjustment because it can significantly improve the manufacturing yield. The number of redundant vias inserted in the circuit design is a metric which can be conveniently measured, and EDA tools are often compared with one another based on this metric.
Unfortunately, conventional techniques for inserting redundant vias are ad-hoc in nature and do not add sufficient number of vias. Furthermore, when redundant vias are added, the resistance and capacitance of circuit elements can change. Hence, when a redundant via is added after timing optimization, the system may need to perform another round of timing optimization to account for any changes in the timing characteristics.